1. Field of the Invention
The present invention relates to simulation of circuit design and in particular to the combined dynamic and static simulation of a circuit design.
2. Discussion of the Related Art
Electronic design automation (EDA) is now commonly used in the design of integrated circuits. EDA makes extensive use of computers to automate the design process. Once a circuit has been designed and physically laid out, extensive testing is performed to verify that the new design and layout will work as desired. Testing of the new design is typically performed by simulating the design using a computer, which permits relatively fast verification of the circuit without necessitating physically placing the design in silicon.
Static analysis and dynamic simulation are two primary conventional methods employed to analyze and verify circuit behaviors of a design. Static analysis and dynamic simulation are described generally in Robert B. Hitchcock et al., xe2x80x9cTiming Analysis of Computer Hardware,xe2x80x9d IBM J. Res. Develop., vol. 26, No. 1, pp. 100-105, January 1982; and A. Vladimirescu, K. Zhang, A. Newton and D. Pederson, xe2x80x9cThe SPICE Circuit Simulator, SPICE Version 2G User""s Guidexe2x80x9d EECS Dept. of U. C. Berkely, August 1981, respectively, both of which are incorporated herein by reference.
Both approaches, however, are appropriate for only certain blocks and both have limitations. Conventionally, static analysis techniques are used on digital circuits. Static analysis has the advantage that input vectors are not used and therefore do not need to be specified by the user. Instead, static analysis is based on worst-case analysis to determine the worst-case delay of the circuit. The critical paths can be determined by propagating a transition through the circuit based on worst-case assumptions. However, because static analysis does not consider concurrent updates of all the signals of the entire circuit, some critical paths that are reported may never happen. This is the so-called xe2x80x9cfalse pathsxe2x80x9d problem of static timing analysis. False paths are described in more detail by D. Brand and V. S. Iyengar in xe2x80x9cTiming analysis using functional relationships,xe2x80x9d IEEE ICCAD ""86. Dig. of Tech. Papers, Santa Clara, Calif. pp. 126-129, November 1986, which is incorporated herein by reference.
An additional limitation of static analysis is that it cannot be used for analog circuits and it has poor accuracy for delay sensitive parasitic elements. Moreover, static analysis has difficulties handling simultaneous input changes, cannot capture incomplete transitions or glitches, and is difficult to use for asynchronous circuits.
Dynamic simulation, on the other hand, is conventionally used on analog circuits. Dynamic simulation applies input vectors, i.e., particular input patterns, to the simulated circuit to determine the resulting output of the circuit. While dynamic simulation can provide higher accuracy than static analysis, dynamic simulation requires a long simulation times because a large number of input vectors must be simulated in order to achieve the true best and worst case results for circuitry having a large number of inputs. In addition, dynamic simulation only provides incomplete worst-case coverage. Moreover, it is difficult to estimate typical power consumption using dynamic simulation.
Silicon technology has advanced to the state that single chips can now be built with more than tens of millions of transistors. This technology promises new levels of integration into a single chip. Circuit designs are expected to increasingly mix analog circuitry, digital circuitry and memory blocks into a single chip, i.e., a system-on-a-chip (SOC). By way of example, FIG. 1 shows a block diagram of a SOC circuit 10 that includes analog circuitry 12, Random Access Memory (RAM) 14, Read Only Memory (ROM) 16 and a digital logic core 18. The combination of mixed analog and digital design, however, requires sophisticated simulation techniques. In particular, a mixed analog/digital simulator must provide both performance for large digital circuitry and accuracy for critical analog circuitry. Neither static analysis nor dynamic simulation can provide the desired performance and accuracy required for simulating mixed analog and digital circuitry.
Thus, there exists a need for an analysis tool for simulating circuit designs that include analog and digital features and that provides the performance of static analysis and the accuracy of dynamic simulation.
A method and system for simulating a circuit design, which may include analog and digital circuitry, uses a hybrid system of static analysis and dynamic simulation. The hybrid simulation system solves problems associated with traditional static and dynamic approaches, while maintaining the accuracy advantage of dynamic simulation and efficiency advantage of static analysis.
The hybrid simulation system, in accordance with the present invention, reads in the net list of the user""s circuit design, partitions the circuit design into a plurality of stages, then applies the input vectors. The hybrid simulation system uses a unique hybrid vector notation, where a hybrid vector can represent a number of possible static signal states, i.e., a logic 0 or logic 1, as well as a number of possible dynamic signal transitions, i.e., a rising signal or a falling signal. The possible combinations of states and transitions are enumerated and the network in the stage is solved for all possible combinations. The results from the network solutions for all the different combinations of states and transitions are recomposed into the hybrid notation, which is then applied to the next stage.
The hybrid simulation system in accordance with the present invention includes storing device information and node connectivity of the circuit design and partitioning the circuit design into a plurality of stages. At least one input vector is applied to the stage, wherein at least one input vector is a hybrid vector that represents a plurality of possible signal states. The possible combinations of signal states of the at least one input vector in the stage are enumerated and the network in the stage is solved for all the possible combinations of signal states. The output of the stage is updated with an output vector, which may also be a hybrid vector that represents a plurality of possible signal states. The hybrid vector can also represent a plurality of possible signal transitions in addition to a plurality of possible signal states.
The hybrid simulation system may further include applying one of patterns of the possible combinations of signal states and signal transitions to the stage and solving the network in the stage for that pattern. The resulting output vector is stored in an output array of patterns of possible combinations of signal states and signal transitions. The acts of applying one of the patterns to the stage, solving the network for the stage and storing the result in the output array are repeated until all the patterns have been applied and solved. The output vectors for the stage are then updated by recomposing the possible patterns from the output array into output vectors that represent a plurality of possible signal states and possible signal transitions. The output vectors for the current stage may represent an input vector for the next stage and hence trigger the simulation of the next stage.
The process continues for each stage until a final output for the user""s circuit design is achieved. The enumeration and analysis of some stages may be skipped under isome conditions. For example, if the input vectors are changing into a superset of the previous vector, and the output vector of the stage represents all possible signal transitions. A state is a superset of another state if the second state represents a plurality of possible signal states (or signal transitions), one of which is the same as the first state.
The enumeration can be skipped, but the analysis still performed, if each input vector to the stage represents only one possible signal state, or if the input vector has changed from the previous state, then both the current and previous states represent only one possible signal state and all prior input vectors represent only one possible signal state.
In addition, the hybrid simulation system advantageously reduces effective size of large stages by further partitioning, which decreases the time required to analyze the stage. The further partitioning is performed based on the mutual exclusivity of controlling nodes within the large stage. The devices with mutual exclusive controlling nodes are broken apart to from sub-stages. After enumerating the possible combinations from the input vectors, the hybrid simulation system dynamically recombines those sub-stages that are non-mutually exclusive with the controlling signal of the triggering input devices. Analysis is then performed on the recombined sub-stages. Additionally, false state input enumeration is eliminated in accordance with the present invention by combining affected stages into a complex cell. The enumeration is performed at the complex cell level, while the analysis is performed at the constituent stage level.
The hybrid simulation system of the present invention may be a computer implemented method of simulating a circuit design, that includes analog and digital circuitry, or it may be incorporated into a computer-usable medium having computer-readable program code embodied in a device for causing a computer to perform the hybrid simulation.